Backend support evidence

Backend matrix

The Wide AVX2 backend is a static build selection. The build accepts it only with FLYOLOGY_SIMD_ARCH=x86_64 and FLYOLOGY_SIMD_AVX2=enabled. The static operations perform no runtime feature check. Before a target runs this build, CPUID must report the AVX, AVX2, and OSXSAVE bits, and XCR0 must enable XMM and YMM register state. The complete-array and whole-buffer AVX2 algorithms use a separate runtime feature gate.

The public CI workflow shows the current hosted result. “CI configuration” in this table describes the job that the repository defines. Check the workflow result before you treat that job as successful.

Not every operation maps to one instruction

On AArch64, the Advanced SIMD sequence for the U64x2 and I64x2 wrapping-multiplication overloads splits each lane into low and high 32-bit parts. It combines the low-by-low product with the low 32 bits of the low-by-high and high-by-low cross-products. The result is modulo 2⁶⁴.

For signed 32- and 64-bit saturation, SSE2 derives an overflow mask and selects the signed minimum or maximum. Unsigned saturating addition derives a carry mask and selects the unsigned maximum. Unsigned saturating subtraction derives a borrow mask and selects zero.

For I64x2 arithmetic right shift, SSE2 derives a sign mask for each lane. It applies a logical right shift to each 64-bit lane and its sign mask, then merges the sign fill.

All integer reductions use fixed-shuffle SSE2 trees. Floating Reduce_Add starts from positive zero and adds lanes in ascending order because floating-point addition is not associative. Floating Min_Number and Max_Number classify IEEE encodings and select lane bits with integer SSE2 operations. The Reduce_Min_Number and Reduce_Max_Number sequences start with lane 0. They classify each remaining lane and select the result bits in ascending lane order.

The 27 integer Widen_Low, Widen_High, Narrow_Truncate, and Narrow_Saturate overloads use the operation- and type-specific Advanced SIMD and SSE2 mechanisms in the table. The eight same-width signed/unsigned conversions use the listed clamp-and-select mechanisms. Floating widening and narrowing and integer/floating conversions use separate target sequences. The 64-bit numeric conversions process each lane separately. Floating-to-integer conversions classify inputs for saturation. Unsigned numeric conversions apply an additional correction across 2 to the power of 63.

For all 16 lane-preserving Bit_Cast overloads, the AArch64 and x86-64 backends reinterpret the complete private 128-bit value directly. They do not call the portable root Bit_Cast operation. This internal lowering does not make the private vector representation part of the public contract.

Wide bit casts and conversions have no dedicated 256-bit instruction claim. The optional x86-64 AVX2 byte operations, floating arithmetic, and lane-movement mechanism have the 256-bit claims in the table. The AArch64 lane-movement mechanism has the per-half tbl claims in its three rows.

Compiler scope

The executed compiler evidence uses GNAT FSF 16.1.0. GCC-based GNAT is the initial required compiler family.

GNAT LLVM remains a compatibility target. It is not an implemented or tested backend in this release.

Continuous checks

The workflow runs checked and release builds. Semantic checks include deterministic differential tests, independent lane oracles, full-width pseudorandom integer data, and floating-point edge cases.

The 16-entry table-lookup tests exhaustively cover index values from zero through 255. Deterministic pseudorandom cases compare every scalar and Native result lane with an independent expectation. A public caller probe requires the Native operation and rejects the portable root operation. The AArch64 exact-symbol gate requires tbl. The x86-64 gate requires 16 comparisons, 16 table-byte broadcasts, 16 masks, 16 merges, and zero initialization. Both exact-symbol gates reject portable and out-of-line lookup calls. The Native-object gate rejects a retained portable lookup call.

Selection tests cover every mask pattern for all ten 128-bit value types. An independent lane oracle checks both scalar and Native results. Floating checks compare the selected bits. The AArch64 code-generation gate requires one cmtst mask expansion and one bsl selection in each generated subprogram. It rejects portable selection calls.

Independent modular-bit lane oracles cover all 24 fixed-width Add_Wrap, Subtract_Wrap, and Multiply_Wrap overloads. U8x16 uses fixed cases and 2,000 deterministic full-width input pairs; each of the other seven integer types uses fixed cases and 250 pairs. Every case checks the root, Backends.Scalar, and Backends.Native results. Directed 64-bit cases cover partial-product boundaries. A generated public caller probe covers every overload. Each caller must enter its matching Backends.Native operation, and each exact-leaf gate requires the operation- and type-specific Advanced SIMD or SSE2 sequence. The gates reject root, Scalar, Wide, mismatched Native, and out-of-line helper routes.

Independent lane oracles cover 16 fixed-width saturating-arithmetic overloads in total: eight Add_Saturate and eight Subtract_Saturate overloads. Each non-U8 integer type uses fixed clamp-boundary inputs and 250 deterministic full-width input pairs. The focused U8x16 suite uses fixed inputs and 2,000 deterministic full-width input pairs. Every case checks the root, Backends.Scalar, and Backends.Native results. A generated public caller probe covers every overload. Each caller gate requires one relocation to the matching Backends.Native overload and exactly one out-of-line branch; it rejects root, Scalar, Wide, and mismatched routes. Exact-leaf gates bind operand and result transfers, require the operation- and type-specific Advanced SIMD or SSE2 sequence, and reject branches to out-of-line helpers.

Independent bitwise lane oracles cover all 32 fixed-width integer Bitwise_And, Bitwise_Or, Bitwise_Xor, and Bitwise_Not overloads. Directed inputs cover zero, all-one, alternating, and sign-bit patterns. U8x16 uses fixed cases and 2,000 deterministic full-width input pairs; each of the other seven integer types uses fixed cases and 250 pairs. Every case checks the root, Backends.Scalar, and Backends.Native results. A generated public caller probe covers every overload. The U8x16 Bitwise_And caller must contain the exact inlined target operation; each other caller must call exactly one matching Backends.Native overload. Caller gates reject root, Scalar, Wide, and mismatched Native routes. Exact-leaf gates bind operand and result transfers, require the matching Advanced SIMD or SSE2 operation, and reject out-of-line helpers.

Independent lane oracles cover 16 fixed-width integer overloads in total: eight Min and eight Max overloads. Each non-U8 integer type uses fixed inputs and 250 deterministic full-width input pairs. Directed U64x2 and I64x2 cases cover top-bit boundaries and values with equal high words but different low words. The focused U8x16 suite uses fixed inputs and 2,000 deterministic full-width input pairs. Every case checks the root, Backends.Scalar, and Backends.Native results. A generated public caller probe covers every overload. Each caller gate requires exactly one call to the matching Backends.Native overload and rejects root, Scalar, Wide, and mismatched routes. Exact-leaf gates bind operand and result transfers, require the operation- and type-specific Advanced SIMD or SSE2 sequence, and reject branches to out-of-line helpers.

Independent lane expectations cover all 50 canonical fixed-width lane arrangements. The focused U8x16 suite uses fixed and 2,000 deterministic inputs; each of the other nine value types uses fixed and 250 full-width inputs. Every case checks the root, Backends.Scalar, and Backends.Native result. Floating cases use raw encodings and compare every moved bit. A generated public caller probe covers every overload. Each caller gate requires one matching Backends.Native call and rejects root, Scalar, Wide, and mismatched Native calls. Each exact-leaf gate binds the operand and result transfers, requires the operation- and type-specific Advanced SIMD or SSE2 sequence and any applicable immediate, and rejects branches to out-of-line helpers.

For all eight integer types, tests apply independent bit-level oracles to scalar and Native logical shifts. They test every count from zero through two positions beyond the applicable lane width and Natural'Last. They also use deterministic full-width inputs. Exact-symbol gates require NEON ushl for every AArch64 overload. On x86-64, they require byte widening and repacking or the applicable packed word, doubleword, or quadword shift. The gates reject portable Zero, Shift_Left_Logical, and Shift_Right_Logical calls.

For all four signed integer types, tests apply independent arithmetic-right-shift oracles to every count from zero through two positions beyond the applicable lane width and Natural'Last. Each type also uses 250 deterministic full-width inputs. Exact-symbol gates require NEON sshl for each AArch64 overload. The x86-64 gate requires byte widening, psraw, and repacking for the 8-bit overload. It requires psraw for the 16-bit overload and psrad for the 32-bit overload. For the 64-bit overload, it requires sign-mask derivation, logical right shifts, and sign-fill merging. A combined public caller probe covers all 20 Native shift overloads. It rejects portable Shift_Left_Logical, Shift_Right_Logical, and Shift_Right_Arithmetic calls. The Native-object gate rejects the same portable shift calls.

For all ten 128-bit value types, independent lane expectations check scalar and Native lane slides. They cover every count from zero through two positions beyond the applicable lane count and Natural'Last. Each type also uses 250 deterministic pseudorandom inputs. Floating cases use raw special encodings and compare retained bits. A dynamic public caller probe covers all 20 Native overloads. Exact-symbol gates inspect every dispatcher. Constant-count probes verify that representative immediate leaves inline into callers. These gates and the Native-object gate reject portable Zero, Slide_Lanes_Toward_Low, and Slide_Lanes_Toward_High calls.

Floating unordered-comparison tests use an independent IEEE encoding oracle. Fixed cases cover quiet and signaling NaNs in either or both inputs, NaN encodings with both sign-bit values, infinities, and signed zero. Another 250 deterministic cases use raw binary32 and binary64 encodings. A public caller probe covers both exact overloads. The AArch64 code-generation gate requires two comparisons in which each input is compared with itself, bitwise mask AND, and inversion. It rejects portable and out-of-line comparison calls.

The conversion tests cover integer truncation and saturation boundaries. Same-width conversion cases cover negative signed inputs around zero and unsigned inputs around the signed maximum. Independent lane and bit oracles use 512 deterministic full-width inputs and directly check the root, Backends.Scalar, and Backends.Native result of every explicit conversion overload. A generated public caller probe covers all 35 integer lane-width and signedness conversions. Each caller requires exactly one matching Backends.Native relocation and one out-of-line branch; the gates reject root, Scalar, Wide, and mismatched Native routes. AArch64 exact-leaf gates bind source and result transfers and require the exact widening, narrowing, or clamp sequence. The x86-64 gates bind source and result transfers and require the operation- and type-specific SSE2 instruction classes. Both reject branches or out-of-line helpers inside the selected leaf.

The tests cover F32 widening for signed zeros, subnormal and normal boundaries, infinities, and NaNs. Binary64 narrowing cases cover positive and negative halfway values, maximum finite binary32 values, overflow, gradual underflow to binary32 subnormals, underflow to signed zero, infinities, and NaNs. The x86-64 code-generation gate checks both floating widening overloads and the floating narrowing overload. It requires cvtps2pd, the high-half shuffle, two cvtpd2ps conversions, and the lane merge. It rejects scalar or out-of-line conversion calls.

Integer-to-floating cases use an independent bit-level rounding oracle with deterministic, full-width pseudorandom inputs. Floating-to-integer cases use a separate bit-level oracle and raw pseudorandom floating encodings. On x86-64, a control-state test runs the signed and unsigned binary32- and binary64-to-integer conversions under all four MXCSR rounding modes. It checks identical scalar and Native results, verifies that each selected mode remains set, and restores the original control word. The x86-64 code-generation gate inspects all four conversions between 32-bit integer and binary32 lanes. It requires cvtdq2ps or cvttps2dq with the applicable correction, classification, and selection instructions. It rejects scalar conversion calls and writes to the floating-point control register.

A separate public caller probe covers all four conversions between 64-bit integer and binary64 lanes. The x86-64 gate requires two conversion instruction sites for each signed overload. Each unsigned overload has four sites because each lane has a direct path and a corrected path for values at or above 2⁶³. The gate also requires lane advancement and merging, signed-range classification, and the exact unsigned corrections. It rejects portable conversion calls, out-of-line helpers, and floating-point control writes.

Scalar and Native tests cover aligned, misaligned, and out-of-range inputs for the nine typed 128-bit alignment predicates and all ten Wide predicates. The out-of-range cases use Natural'Last and return false without evaluating an element address. A public caller probe covers all 19 typed overloads and rejects portable or out-of-line alignment-predicate calls. The Native-object gate permits only the shared root Byte_Array Is_Aligned_16 contract predicate.

Independent lane and array oracles cover all 60 complete 128-bit memory overloads. Fixed inputs and 250 deterministic inputs per type check root, Backends.Scalar, and Backends.Native loads and stores. Store checks preserve sentinel elements outside the complete-vector extent. Floating cases use deterministic raw encodings and directed signed-zero, subnormal, infinity, quiet-NaN, and signaling-NaN encodings.

A generated public caller gate covers all 60 overloads on AArch64 and x86-64. Each caller must use the matching selected Backends.Native operation and overload suffix. The gates reject root, Backends.Scalar, mismatched Backends.Native, and Wide operation calls. Exact-leaf gates require the matching ldr q and str q or movdqu and movdqa transfers. They reject portable, Scalar, and Wide memory helpers.

For all ten 128-bit value types, partial-memory tests check every valid count against independent lane and array expectations. Floating loads verify positive-zero fill by its complete bit encoding. Zero-count cases use Start = Natural'Last and confirm that no element address is evaluated. Protected-page tests place every scalar and Native byte tail next to an inaccessible page. A public caller probe covers all 20 Native overloads, and a Native-object gate rejects calls to the portable partial-memory operations. AddressSanitizer provides another boundary check where the toolchain supports it.

The 80 Wide Native memory overloads comprise full, unaligned, aligned, and partial load and store operations for all ten value types. Independent lane and array oracles check fixed inputs and 128 deterministic inputs per type. Floating cases compare raw bit encodings. Partial cases cover every count, preserve sentinel elements outside the store extent, and use Start = Natural'Last for a zero count. Protected-page tests cover every Wide byte count from 0 through 32.

A generated caller gate covers all 80 Wide overloads. Each caller must use only its matching selected 128-bit operation families and overload suffixes, without a Wide dispatcher. The AArch64 and x86-64 gates also reject portable root operations. In a scalar build, the selected U8x16 Load_Unaligned rename resolves to the portable root operation. The exact AArch64 check for the inlined U8x32 Load_Unaligned caller requires two ldr q loads and two str q result stores.

Independent per-lane bit oracles check all 16 Bit_Cast overloads with 512 deterministic full-width inputs. Directed cases cover zero, high-bit and alternating integer encodings, signed zeros, subnormals, infinities, and quiet and signaling NaNs with both sign-bit values. Scalar and Native results must preserve every lane bit. A public caller probe covers all 16 Native overloads. The Native-object gate rejects calls to the portable root Bit_Cast operation and out-of-line helpers whose symbols contain native_bit_cast.

A contract-parity gate compares the 588 declarations in Backends.Scalar with the matching 588 declarations in Backends.Native. It fails when a primitive overload exists in only one backend contract.

Mask patterns and Population_Count, First_True, and Last_True results are exhaustive for each 128-bit mask width. Independent Wide mask-reduction oracles cover zero, all, alternating, the first and last lanes, and both private-half boundaries. They exhaust all masks for the 4-, 8-, and 16-lane shapes and use 1,024 deterministic pseudorandom masks for the 32-lane shape. Public caller probes cover all four 128-bit mask shapes. Exact-symbol gates require AArch64 byte population count, horizontal sum, bit reversal, and leading-zero count. The x86-64 gates require fixed-width arithmetic and forward and reverse bit scans without POPCNT. They reject portable mask-reduction calls.

The AArch64 and x86-64 backends apply construction, conversion, Boolean algebra, lane tests, and Boolean queries directly to the fixed-width integer bits of all four 128-bit compact-mask shapes. A scalar build uses the portable scalar implementation. The 4- and 2-lane shapes mask unused storage bits. Exhaustive tests check every logical mask and every Test result against independent integer expectations. Fixed cases set unused high bits in the Mask_From_Bit_Mask input and verify that the result excludes them. A generated public-caller probe covers all 40 operation and shape pairs. The two Mask_8x16 bit-conversion callers are verified inline. Each of the other 38 callers requires one matching Backends.Native overload and one out-of-line branch. Caller and Native-object gates reject root, Scalar, Wide, and mismatched mask-operation routes.

For all ten 128-bit value types, independent construction checks verify every lane of Zero and Splat. Fixed integer cases cover the lane-type limits. Floating checks compare signed zero, infinity, subnormal, quiet-NaN, and signaling-NaN encodings bit for bit. Deterministic full-width inputs exercise each lane. A public caller probe covers every overload. For AArch64, exact-symbol gates require direct Zero construction and NEON dup for Splat. For x86-64, they require the corresponding SSE2 zeroing and lane-width broadcast sequences. The gates reject portable construction calls.

For all ten 128-bit value types, independent lane-array checks cover From_Lanes, To_Lanes, Extract, and Replace. They verify every constructed, returned, extracted, preserved, and replaced lane. Floating checks compare complete bit encodings. Deterministic full-width inputs exercise each position. A public caller probe covers all 40 overloads. A Native-object gate rejects calls to the portable lane-access operations.

All 60 Wide construction and lane-access overloads compose selected 128-bit operations. Zero, Splat, From_Lanes, and To_Lanes apply the matching operation to both private parts. To_Lanes concatenates the low-part lanes before the high-part lanes. Extract and Replace apply the matching operation only to the part that contains the requested lane. Replace preserves the other part. A scalar build uses the same composition through the portable 128-bit implementation.

Independent store- and load-backed lane-array checks cover fixed inputs and 128 deterministic inputs for each Wide type. Floating checks use raw bit patterns. The checks cover every returned, extracted, preserved, and replaced lane for both the scalar Wide implementation and Wide.Native. A generated caller probe covers all 60 overloads in each target configuration. The gates require matching selected 128-bit calls or verified inline U8 Splat code. They require the private-half boundary and a high-half lane adjustment for Extract and Replace. They reject mismatched selected operations, portable calls, and Wide dispatchers.

The Wide compact-mask family has 52 overloads: Mask_From_Bit_Mask, To_Bit_Mask, Mask_And, Mask_Or, Mask_Xor, Mask_Not, Test, Any_True, All_True, None_True, Population_Count, First_True, and Last_True for each of four mask shapes. The AArch64, composed x86-64, and optional AVX2 configurations apply each matching selected 128-bit operation to both private parts, except that Test selects only the containing part. Ada combines compact bits, Boolean query results, counts, and positions. A scalar build uses the same composition through portable 128-bit operations.

Independent integer-bit oracles exhaust all masks for the 4-, 8-, and 16-lane shapes and use 1,024 deterministic masks for the 32-lane shape. Each case also uses another deterministic mask and checks scalar Wide and Wide.Native AND, OR, XOR, complement, lane tests, queries, population count, and positions. A generated caller probe covers all 52 overloads. The two 32-lane bit-conversion callers are verified inline identities. Every other non-Test caller requires two exact matching selected operations. Each Test caller requires either two part-specific calls or one compiler-merged selected call, plus the half condition and high-half lane adjustment. The gates reject portable, Scalar, Wide dispatcher, and mismatched mask-operation routes.

The Wide integer family has 24 wrapping-arithmetic overloads in total: eight each of Add_Wrap, Subtract_Wrap, and Multiply_Wrap. AArch64 and the composed x86-64 backend apply the matching selected 128-bit operation to both private parts. The optional AVX2 backend uses isolated vpaddb and vpsubb leaves for byte addition and subtraction. Its byte-multiplication leaves use vpmullw, vpand, vpsrlw, vpsllw, and vpor. All six byte leaves run vzeroupper. For the other 18 overloads, the optional AVX2 backend retains the two-part selected composition. A scalar build uses the same composition through the portable 128-bit implementation.

Independent modular-bit lane oracles check fixed wrapping boundaries and 128 deterministic full-width input pairs for each Wide integer type. They check the scalar Wide implementation and Wide.Native results. A generated caller probe covers all 24 overloads in each target configuration. The AArch64, composed x86-64, and non-byte AVX2 gates require two relocations to the exact matching selected 128-bit operation and exactly two out-of-line branches. Each byte AVX2 caller gate requires one matching isolated leaf and exactly one out-of-line branch. The caller gates reject mismatched selected operations, portable calls, Scalar calls, Wide dispatchers, and the general byte mechanism.

The Wide integer family has 16 saturating-arithmetic overloads in total: eight Add_Saturate and eight Subtract_Saturate overloads. AArch64 and the composed x86-64 backend apply the matching selected 128-bit operation to both private parts. The optional AVX2 backend uses isolated vpaddusb, vpsubusb, vpaddsb, or vpsubsb leaves for the four byte overloads. For the other 12 overloads, the optional AVX2 backend retains the two-part selected composition. A scalar build uses the same composition through the portable 128-bit implementation.

Independent lane oracles check fixed clamp boundaries and 128 deterministic full-width input pairs for each Wide integer type. They check the scalar Wide implementation and Wide.Native results. A generated caller probe covers all 16 overloads in each target configuration. The AArch64, composed x86-64, and non-byte AVX2 gates require two relocations to the exact matching selected 128-bit operation and exactly two out-of-line branches. Each byte AVX2 caller gate requires one matching isolated leaf. The byte leaf gates require the matching packed AVX2 saturation instruction and vzeroupper. The caller gates reject mismatched selected operations, portable calls, Scalar calls, Wide dispatchers, and the general byte mechanism.

The Wide integer family has 32 bitwise overloads in total: eight each of Bitwise_And, Bitwise_Or, Bitwise_Xor, and Bitwise_Not. AArch64 and the composed x86-64 backend apply the matching selected 128-bit operation to both private parts. For the eight byte overloads, the optional AVX2 backend uses isolated vpand, vpor, or vpxor leaves. Each AVX2 Bitwise_Not leaf constructs an all-one mask with vpcmpeqd and complements with vpxor. All eight byte leaves run vzeroupper. For the other 24 overloads, the optional AVX2 backend retains the two-part selected composition. A scalar build uses the same composition through the portable 128-bit implementation.

Independent bitwise lane oracles check zero, all-one, alternating, and sign-bit patterns. They also check 128 deterministic full-width input pairs for each Wide integer type. Every case checks the scalar Wide implementation and Wide.Native results. A generated caller probe covers all 32 overloads in each target configuration. The AArch64 and composed x86-64 gates verify two inline target operations for U8x32 Bitwise_And. The other composed and non-byte AVX2 gates require two relocations to the exact matching selected 128-bit operation and exactly two out-of-line branches. Each byte AVX2 caller gate requires one matching isolated leaf and exactly one out-of-line branch. The caller gates reject mismatched selected operations, portable calls, Scalar calls, Wide dispatchers, and the general byte mechanism.

The Wide integer family has 16 Min and Max overloads in total: eight of each operation. AArch64 and the composed x86-64 backend apply the exact matching selected 128-bit operation to both private parts. For the four byte overloads, the optional AVX2 backend uses isolated vpminub, vpminsb, vpmaxub, or vpmaxsb leaves. Each byte leaf runs vzeroupper. For the other 12 overloads, the optional AVX2 backend retains the two-part selected composition. A scalar build uses the same composition through the portable 128-bit implementation.

Independent lane oracles check signedness boundaries, top-bit transitions, alternating 16#AA# and 16#55# byte patterns, and 128 deterministic full-width input pairs for each Wide integer type. Every case checks the scalar Wide implementation and Wide.Native results. A generated caller probe covers all 16 overloads in each target configuration. The AArch64, composed x86-64, and non-byte AVX2 gates require two exact selected 128-bit routes and two out-of-line branches. On composed x86-64, each signed-byte route is verified after inlining as two signed comparisons and two value selections. Each byte AVX2 caller gate requires one matching isolated leaf, exactly one out-of-line branch, and no selected Native route. The byte leaf gates require the operation- and signedness-specific packed instruction and vzeroupper. The caller gates reject mismatched selected operations, portable calls, Scalar calls, Wide dispatchers, and the general byte mechanism.

The Wide integer family has 20 shift overloads in total: Shift_Left_Logical, Shift_Right_Logical, and Shift_Right_Arithmetic. Each logical operation supports all eight integer types. The arithmetic operation supports the four signed integer types. The AArch64, composed x86-64, and optional AVX2 configurations apply the exact matching selected 128-bit operation to both private parts. A scalar build uses the same two-part composition through the portable 128-bit implementation.

Independent bit-level lane oracles check zero, all-one, alternating 16#AA# and 16#55# byte patterns, and sign-bit patterns. They check every count from zero through two positions beyond the applicable lane width and Natural'Last. The oracles require zero from oversized logical shifts and full sign fill from oversized arithmetic right shifts. They also check 128 deterministic full-width vectors for each Wide integer type. Every case checks the scalar Wide implementation and Wide.Native results. A generated caller probe covers all 20 overloads in each target configuration. Each caller gate requires two relocations to the exact matching selected 128-bit operation, exactly two selected Native routes, and exactly two out-of-line branches. The gates reject mismatched selected operations, portable calls, Scalar calls, and Wide dispatchers.

The 62 Wide comparison and selection overloads are Equal, Less_Than, Less_Equal, Greater_Than, Greater_Equal, and Select_Value for all ten value types, plus Unordered for both floating types. AArch64 and the composed x86-64 backend apply the matching selected 128-bit operation to both private parts. The optional AVX2 backend retains its isolated byte comparison and selection mechanisms. A scalar build uses the portable Wide implementation.

Independent lane oracles cover fixed inputs and 128 deterministic inputs for each Wide type. Integer cases use full-width values. Floating cases use raw bit patterns that include quiet and signaling NaNs with both sign-bit values, infinities, subnormals, and signed zero. The lane oracles check Equal, all four ordered comparisons, and Unordered for both the scalar Wide implementation and Wide.Native. The Select_Value checks compare all bits of each selected floating encoding. A generated caller probe covers all 62 overloads in each target configuration. The gates verify the matching two-part lowering, or the applicable isolated or inlined byte lowering. They reject mismatched selected operations, portable calls, and Wide dispatchers.

The 128-bit exact byte-sum tests use a fixed maximum vector and 2,000 deterministic pseudorandom vectors. An independent lane-array oracle checks both scalar and Native results. The exact-symbol gates require uaddlv and result transfer on AArch64. On x86-64, they require psadbw, transfer of the high partial sum, and 64-bit addition. Both gates reject calls to the portable sum.

The 128-bit and Wide byte-table tests cover every unsigned byte index, a fixed mixed mapping, and deterministic pseudorandom tables and indexes. An independent lane oracle defines both results. AArch64 code-generation checks require one-register tbl for the 16-entry operation and two-register tbl for each half of the Wide operation.

The composed x86-64 and scalar Wide mechanisms use one selected 128-bit Splat to construct a vector whose lanes all contain 16. They use four selected 128-bit Table_Lookup operations, two selected 128-bit Subtract_Wrap operations, and two selected 128-bit Bitwise_Or operations. The low-table lookup returns zero above 15. After subtraction of 16, the high-table lookup returns zero for every original index outside 16 through 31. The merge therefore returns zero for an original index above 31. The x86-64 gate verifies four selected 128-bit Table_Lookup calls, two selected 128-bit Subtract_Wrap calls, and two selected 128-bit Bitwise_Or calls. It rejects portable and public Wide lookup calls.

The x86-64 Wide AVX2 lookup runs the same differential cases. Its code-generation gate requires one mechanism call from the public caller. The isolated implementation subprogram must contain vpshufb, vperm2i128, vpsubusb, and vzeroupper. Baseline objects must contain no AVX instruction.

The Wide byte tests use literal wrap, saturation, and signedness boundaries for U8x32 and I8x32. Deterministic pseudorandom cases compare all selected arithmetic, bitwise, minimum, and maximum operations with independent lane results. The x86-64 code-generation gate inspects all 22 AVX2 overloads and requires vzeroupper in each isolated subprogram. The multiplication checks require vpmullw, masks, and word shifts because AVX2 has no packed byte multiply instruction.

The Wide floating tests use independent lane oracles for the four arithmetic overloads and the Min_Number and Max_Number overloads at each width. Cases cover fixed finite values, IEEE special categories, both signed-zero orders, 128 deterministic finite vectors, and 128 raw-bit vectors per type. The x86-64 gate requires one isolated leaf call from every public caller. Arithmetic leaf checks require the matching packed instruction. Minimum and maximum checks require integer classification and bit selection and reject floating minimum, maximum, or comparison instructions. Every leaf requires vzeroupper. The checks reject portable, composed, and out-of-line calls.

For both signed and unsigned bytes, the tests check all 65,536 ordered input pairs against an independent lane oracle for equality and the four ordered comparisons. Selection tests cover each individual mask lane, six fixed masks, and deterministic pseudorandom masks. The AVX2 code-generation gate requires packed byte equality, packed signed greater-than, compact mask extraction, mask expansion, Boolean lane selection, and vzeroupper. The unsigned greater-than check also requires two sign-bit bias transformations. The gate checks one isolated mechanism call from each public byte-comparison and selection probe.

An independent lane oracle checks scalar and Native permutation results for all ten value types. Fixed cases cover default maps, broadcasts, and both source choices. Each type also uses 250 pseudorandom one-source maps and varied deterministic two-source maps. Floating cases compare special IEEE encodings bit for bit.

The x86-64 public caller gate requires all 20 Native permutation leaves and rejects dispatcher and portable-root calls. Exact-symbol gates require 16 comparison and selector-increment stages for each one-source leaf. They require 32 stages for each two-source leaf and reject calls. AArch64 gates cover all ten types and require one-register or two-register tbl.

The Wide lane-movement checks cover all ten value types:

• Independent lane-array oracles check identity, reverse, broadcast, all-left, all-right, mixed-source, and default maps.
• Each type uses 128 deterministic pseudorandom cases for reverse, interleave, deinterleave, slides, and both Permute_Lanes overloads. Slide checks cover every count. Floating cases use raw encodings and compare moved bits exactly.
• Caller-level gates cover all 90 overloads: seven lane-movement operations and both Permute_Lanes overloads across ten value types. The gates run on AArch64 and both x86-64 Wide selections.
• AArch64 reverse, slide, and one-source Permute_Lanes probes require two tbl operations with two-register tables. Interleave, deinterleave, and two-source probes require two tbl operations with four-register tables. The gates reject dispatcher and per-lane helper calls.
• The composed x86-64 gates require the selected 128-bit permutation and selection calls listed in the table. They reject Wide scalar operation calls.
• The AVX2 reverse, slide, and one-source Permute_Lanes probes require two byte shuffles and one cross-half selection. Interleave, deinterleave, and two-source probes require four byte shuffles and two cross-half selections. Every probe requires vzeroupper and rejects scalar and per-lane helper calls.

The 128-bit compression and expansion tests exhaust every mask pattern for all ten value types. Independent lane oracles check scalar and Native results with deterministic inputs. Floating cases preserve NaNs, infinities, and signed zeros bit for bit. They also check the complete positive-zero encoding in fill lanes.

AArch64 exact-symbol gates require tbl in all 20 compression and expansion overloads. The x86-64 public caller gate covers the same overloads. Each caller must have a relocation to its matching shared SSE2 permutation leaf. It must not call a public Native or portable compact operation. Separate exact-leaf gates cover the ten shared selector comparison, broadcast, mask, and merge sequences and reject calls. The Native-object gate rejects retained portable compression or expansion calls.

The Wide tests use independent lane-array oracles for scalar and Native compression and expansion.

• Mask cases cover zero, all, every one-hot lane, every prefix and suffix length, masks confined to each private half, masks that cross the boundary, alternating masks, and 128 deterministic pseudorandom masks for each value type.
• For floating types, the tests compare the bit patterns of signed zeros, infinities, quiet and signaling NaNs, subnormals, moved lanes, and positive-zero fill lanes.
• AArch64 caller-level probes cover all 20 overloads. Each probe requires one two-register tbl operation for each 128-bit result half. The gates reject out-of-line mask extraction, dispatchers, and per-lane helpers.
• The x86-64 caller-level gate covers all 20 overloads in both composed and AVX2 builds. For each caller, the gate requires two calls to selected 128-bit two-source Permute_Lanes and two calls to selected 128-bit Select_Value. The gate rejects calls to public Native or portable Wide compression and expansion operations.

wide_tests checks all ten Wide value types. It compares scalar and Native arithmetic, comparisons, selection, masks, reductions, lane movement, and slides. Focused evidence for memory and conversions appears in their separate paragraphs.

A separate case sets every lane to 255 and checks the Wide exact byte sum of 8,160. Fixed-vector and deterministic pseudorandom cases compare scalar and Native results with an independent lane oracle. AArch64 and x86-64 caller-level code-generation checks require two calls to the target-selected 128-bit exact byte-sum operation.

The 24 Wide Native integer reductions cover all eight integer families. Independent lane oracles check fixed vectors and 128 deterministic pseudorandom inputs for each family. A generated caller gate covers all 24 overloads. For each caller, it requires two matching selected 128-bit reductions, one matching selected 128-bit Add_Wrap, Min, or Max combine operation, and one matching selected 128-bit extraction. It rejects mismatched selected operations and calls to the Wide and root scalar reductions.

Independent lane oracles cover all 24 128-bit integer reductions. For the seven families other than U8x16, fixed inputs and 250 deterministic full-width inputs check the root, Backends.Scalar, and Backends.Native results. Fixed 64-bit cases cover unsigned wrapping and top-bit boundaries. They also cover signed values with equal high words and different low words. The focused U8x16 suite checks the same three implementations in 2,000 deterministic vector cases.

A generated public caller gate covers all 24 overloads on AArch64 and x86-64. Each caller must call its matching selected Backends.Native reduction. The gate rejects calls to Flyology_SIMD root reductions, Backends.Scalar reductions, mismatched Backends.Native reductions, and Wide or Wide.Native reductions. Exact-leaf gates inspect every operation and integer type. They require the operation-specific Advanced SIMD or SSE2 sequence and reject portable reduction helpers.

The same 2,000 U8x16 vector cases use independent lane, mask, and scalar expectations for wrapping and saturating arithmetic, bitwise operations, comparisons, minimum and maximum, fixed lane arrangements, and integer reductions. A separate Select_Value test exhausts all 65,536 compact masks and checks every lane. Together, these tests cover all 26 operations in the generated Native caller probe. On AArch64 and x86-64, each caller must contain the matching target instruction sequence or call one matching selected Native leaf. The exact selected-leaf check requires the operation-specific target instruction. The gates reject portable root and public Wide dispatcher calls.

The 62 fixed-width comparison and selection overloads are Equal, Less_Than, Less_Equal, Greater_Than, Greater_Equal, and Select_Value for all ten value types, plus Unordered for the two floating types. Independent lane oracles check fixed inputs and 250 deterministic full-width inputs per type for the root, Backends.Scalar, and Backends.Native results. The floating test cases use raw encodings and cover quiet and signaling NaNs, infinities, subnormals, and signed zero. Exhaustive compact masks check selected integer values and floating bits.

A generated public caller probe covers all 62 overloads on AArch64 and x86-64. Each caller enters one isolated matching leaf. For each comparison overload, the exact-leaf gate requires the operation- and type-specific NEON or SSE2 comparison and compact-mask construction. For each Select_Value overload, the gate requires the operation- and type-specific selection sequence. The gates reject calls to portable, Scalar, Wide, mismatched, and out-of-line helper routes.

Independent lane oracles cover all 12 fixed-width floating binary overloads. Fixed inputs and 250 deterministic finite input pairs at each width check the root, Backends.Scalar, and Backends.Native results. Directed IEEE cases cover quiet and signaling NaNs, infinities, signed zero, and division edges. Direct Scalar checks also cover the arithmetic edges and the number-minimum and number-maximum NaN and signed-zero rules.

A generated public caller gate covers all 12 overloads on AArch64 and x86-64. Each caller must call one matching selected Backends.Native operation. The gate rejects root, Backends.Scalar, mismatched Backends.Native, and Wide operation calls. Exact-leaf gates require the matching operation- and type-specific NEON or SSE2 sequence and reject branches or out-of-line helpers.

The independent floating addition oracle starts from positive zero and adds lanes in ascending order. Fixed cases check an input in which every lane is negative zero, signaling-NaN quieting, and a finite binary32 input that distinguishes evaluation order. Exact AArch64 and x86-64 gates require four target additions for F32x4 and two for F64x2. They reject portable reduction calls.

Fixed floating number-minimum and number-maximum cases cover:

• quiet and signaling NaNs in both operand orders;
• both signed-zero orders and infinities;
• distinct signaling-NaN encodings; and
• an input that distinguishes an ascending fold from a reduction tree.

Deterministic ordinary inputs compare each scalar and Native lane with an independent numeric oracle. A separate x86-64 extrema gate inspects the four binary and four reduction overloads. The gate requires integer comparison, classification, shifting, and bit-selection instructions. For reductions, it also requires the expected number of lane-advance shifts. It rejects floating comparisons, floating minimum or maximum instructions, portable calls, and out-of-line helpers.

The six Wide Native floating reductions combine lanes in ascending lane order and do not reduce the private parts independently. Independent lane oracles cover fixed cases, deterministic finite inputs, and deterministic raw floating encodings. They cover NaNs, infinities, signed zero, signaling-NaN order, and the positive-zero addition start.

AArch64 caller-level probes cover all six binary32 and binary64 floating reductions. The code-generation gate requires scalar fadd, fminnm, or fmaxnm sequences in ascending lane order. It verifies the positive-zero or lane-0 start and rejects calls to portable Wide reductions.

The x86-64 gate checks all six composed and AVX2 leaves. It requires the matching scalar addition sequence or the matching integer-only minimum-number or maximum-number classification and bit-selection sequence. It rejects portable Wide and selected 128-bit reduction calls.

Bit-cast round trips cover every pair with the same lane width and count. Floating bit-cast cases preserve special encodings bit for bit.

For the 38 Wide widening, narrowing, and same-width signedness-conversion overloads, tests use fixed vectors and 128 deterministic pseudorandom inputs. Independent integer lane oracles check scalar and Native extension, truncation, saturation, and lane placement. Independent IEEE oracles check specified non-NaN widening and narrowing results bit for bit. When a NaN payload and signaling state are unspecified, they check NaN classification instead. Fixed floating cases cover signed zeros, infinities, quiet and signaling NaNs, subnormals, halfway rounding, and overflow in both private parts.

Caller-level code-generation probes cover all 38 overloads. Each gate requires two calls to the exact matching selected 128-bit operation. Widening gates require one matching low-half call and one matching high-half call. The gates reject mismatched selected operations, portable root operations, and Wide Native dispatcher calls.

The eight Wide conversions between integer and floating lanes also use independent bit-level oracles. Integer-to-floating cases use 128 deterministic full-width integer vectors for each shape. Floating-to-integer cases use 128 deterministic raw floating encodings for each shape. Fixed boundary cases remain in the suite. Caller-level code-generation probes cover all eight overloads. Each gate requires two calls to the exact matching selected 128-bit operation. The gates reject mismatched selected operations, portable root operations, and Wide Native dispatcher calls. The project does not claim a 256-bit instruction sequence.

The protected-page tests place every 128-bit byte-tail count from zero through 16 and every Wide byte-tail count from zero through 32 immediately before an inaccessible page. Whole-buffer tests cover byte Add_Saturate lengths 1 through 160. They also place binary32 and binary64 arrays before that page and run runtime scaling, clamping, AXPY, sums, number extrema, and dot products across full blocks and every tail shape.

Wide code-generation probes require two selected 128-bit calls for binary32 multiplication and binary32-to-unsigned-32 bit casts. Those operations have no 256-bit instruction claim.

AVX2 jobs require executable AVX2 coverage and do not silently skip it.

The workflow does not use continue-on-error.

Current limits

• The public API is experimental.
• The verified compiler matrix contains one GNAT FSF version.
• AVX2-specific 256-bit implementations and code-generation claims cover selected Wide byte operations, F32x8 and F64x4 arithmetic, U8x32 table lookup, lane movement, and both Permute_Lanes overloads.
• The Wide AVX2 backend is selected at build time. On each deployment target, CPUID must report the AVX, AVX2, and OSXSAVE bits, and XCR0 must enable XMM and YMM register state.
• The six AVX2 floating complete-array overloads and seven whole-buffer byte algorithms use a separate runtime feature gate.